1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly, it relates to a forming electrical contact regions between different elements of the integrated circuits without forming surface protection thereon.
2. Description of the Prior Art
FIG. 1 is a block diagram showing an exemplary structure of a general RAM. The structure of such a RAM is disclosed in literature such as IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-18, NO. 5, Oct. 1983. Referring to FIG. 1, a memory cell array 101 is formed by a plurality of word lines and a plurality of bit lines which intersect with each other to be provided with memory cells in respective intersections. A memory cell is selected on the basis of an intersection between a word line selected by an X-address buffer decoder 102 and a bit line selected by a Y-address buffer decoder 103. Indication for writing/reading data in/from the selected memory cell is made by a read/write control signal R/W which is supplied to an R/W control circuit 104. In data writing, input data D.sub.in is inputted in the selected memory cell through the R/W control circuit 104. In data reading, on the other hand, data stored in the selected memory cell is detected by a sense amplifier 105 and thereafter amplified, to be outputted to the exterior through a data output buffer 106 as output data D.sub.out.
FIG. 2 shows an equivalent circuit diagram of a dynamic type memory cell, for illustrating write/read operation for the memory cell.
Referring to FIG. 2, the dynamic memory cell is formed by a field-effect transistor 108 and a capacitor 109. The gate electrode of the field-effect transistor 108 is connected to a word line 110 and a source/drain electrode, which is connected with the capacitor 109, is connected to a bit line 107 respectively. In data writing, the field-effect transistor 108 conducts by application of a prescribed potential to the word line 110, whereby charges applied to the bit line 107 are stored in the capacitor 109. In data reading, on the other hand, the field-effect transistor 108 conducts by application of a prescribed potential to the word line 110, whereby the charges stored in the capacitor 109 are drawn out through the bit line 107.
FIG. 3 illustrates plane layout of a memory part of a dynamic MOSRAM (random access memory) being in folded bitline structure, and FIG. 4 is a sectional view taken along the line. IV--IV in FIG. 3.
The structure of the dynamic MOSRAM is now described with reference to these figures.
The RAM is provided with pairs of MOS transistors and capacitors formed in active regions 112, which are isolated from adjacent elements by isolation oxide films 20 in bottom portions of trenches 18 formed on prescribed positions of the major surface of a semiconductor substrate 3. Each MOS transistor is formed by impurity regions 42 and 44 provided on the major surface of the semiconductor substrate 3 to serve as source or drain regions and a word line 9 for serving as a gate electrode provided through an oxide film 24 on a region between the impurity regions 42 and 44. Each capacitor is formed by an impurity layer 46a connected to the impurity region 44, an impurity layer 46b provided on the side wall of the trench 18 and a cell plate 6 provided on the impurity layers 46a and 46b to also cover the isolation oxide film 20 on the bottom portion of the trench 18 through a capacitor dielectric film 7. An interlayer isolation film 48 is formed by an oxide film to cover the transistor and the capacitor, and a bit line 1 provided on the interlayer isolation film 48 is connected to the impurity region 42 through a contact 12 in a contact hole 49 which is provided in the interlayer isolation film 48.
Such a semiconductor memory device having trench type capacitors is disclosed in "An Isolation-Merged Vertical Capacitor Cell for Large Capacity DRAM", IEDM 1984.
In the RAM of such structure, a prescribed potential is applied to a selected word line 9 to allow conduction of the region between the impurity regions 42 and 44 under the same, thereby to perform read/write operation.
FIGS. 5A to 5H are sectional views schematically showing steps of a method of manufacturing the conventional device.
With reference to these figures, description is now made on such a manufacturing method.
First, an ion which is reverse in conductivity type to a semiconductor substrate 3 is injected into the major surface of the semiconductor substrate 3 and subjected to heat treatment, thereby to form an impurity layer 46a diffused with the ion, being reverse in conductivity type to the semiconductor substrate 3, in a prescribed region (FIG. 5A).
Then an oxide film 50 is formed over the entire major surface of the semiconductor substrate 3, and a trench 18 of prescribed depth is formed on the semiconductor substrate 3, including the oxide film 50 covering a part of the impurity layer 46a. Then a nitride film 52 is deposited over the entire surface including the inner surface of the trench 18, and thereafter the nitride film 52 is partially removed from the bottom surface part of the trench 18 (FIG. 5B).
An ion which is identical in conductivity type to the semiconductor substrate 3 is injected into the bottom surface part of the trench 18, which in turn is thermally oxidized to form an impurity layer 22 diffused with the ion, being identical in conductivity type to the semiconductor substrate 3, and a thick isolation oxide film 20 (FIG. 5C).
The nitride film 52 is removed and an ion which is reverse in conductivity type to the semiconductor substrate 3 is injected into the side wall part of the trench 18 by oblique ion implantation or the like and subjected to heat treatment, thereby to form an impurity layer 46b diffused with the ion being reverse in conductivity type to the semiconductor substrate 3 (FIG. 5D).
The oxide film 50 is removed and a capacitor insulation film 7 is formed over the bottom surface part and the side wall part of the trench 18 and a part of the major surface of the semiconductor substrate 3 through CVD, thermal oxidation or the like. An electrode material such as polysilicon, being mixed with an impurity, is deposited over the entire surface including the inner surface of the trench 18 and an oxide film is further deposited over the entire surface including the inner surface of the trench 18 and subjected to an etchback process through anisotropic etching, thereby to embed an oxide film 54 on the polysilicon material in the trench 18 and flatten the same. At this time, the flattened part is made to expose the polysilicon material. Then a photoengraving process and etching are performed to form a cell plate 6, having a flat surface part of a prescribed configuration, from the polysilicon material (FIG. 5E).
An oxide film 24 for serving as a transfer gate insulation film is formed by thermal oxidation or the like, and films of polysilicon and metal silicide having a high melting point are sequentially laminated on the entire surface to be subjected to a photoengraving process and etching, thereby to form a word line 9. An arsenic (As) ion which is reverse in conductivity type to the semiconductor substrate 3 is injected into exposed major surface parts of the semiconductor substrate 3 and subjected to heat treatment, thereby to form impurity regions 42 and 44 diffused with the ion being reverse in conductivity type to the semiconductor substrate 3 (FIG. 5F).
An oxide film is provided over the entire major surface of the semiconductor substrate 3 including the word line 9 by CVD, to form an interlayer isolation film 48. A resist film 50 is applied onto the entire surface of the interlayer isolation film 48, and an exposure mask 54 is set above the same. The exposure mask 54 is provided with an opening 56, which corresponds to a contact hole to be defined in the interlayer isolation film 48. The exposure mask 54 is exposed to sensitize only a portion of the resist film 50 corresponding to the opening 56, to define an opening 52 for forming the contact hole (FIG. 5G).
The resist film 50 is used as a mask to etch the interlayer isolation film 48 exposed through the opening 52 to reach the major surface of the semiconductor substrate 3, thereby to define a contact hole 49. Phosphorus (P) is injected into the major surface of the semiconductor substrate 3 through the contact hole 49 and diffused by heat treatment, thereby to form an N-type impurity region 58 of high concentration. This impurity region 58 is adapted to prevent punch-through of an aluminum wire, which is formed in a contact hole 12 in a later step, to the semiconductor substrate 3. Finally a film of aluminum, metal silicide having a high melting point or a metal having a high melting point is deposited over the entire surface including the inner surface of the contact hole 49, and patterned to form a bit line 1 which is connected with the impurity region 42 through a contact 12 (FIG. 5H).
In the conventional semiconductor memory device of the above structure, an attempt has been made to improve the degree of integration of the capacitor part by employing a trench type configuration, whereas factors preventing improvement in density and degree of integration have remained in other parts. Namely, the word line 9 must be separated by a prescribed distance from the contact 12 for the following reasons:
(1) When the aluminum wire for serving as the bit line 1 is connected to only the impurity region 42, formed by implantation of As, for serving as a source or drain region of the transistor formed on the major surface of the semiconductor substrate 3 through the contact 12, silicon under the impurity region 42, which is small in depth, is absorbed into the aluminum wire to damage the boundary portion. In order to prevent current leakage from the bit line 1 to the semiconductor substrate 3 caused by such damage, the impurity region 58 is formed by implantation of phosphorus, which is generally larger in diffusivity than As. However, the impurity region 58 is largely spread from the major surface of the semiconductor substrate 3 by heat treatment, not only toward the substrate but also toward the word line 9. Spreading of the impurity region 58 to the channel region under the word line 9 exerts bad influence on the performance characteristic of the transistor. Therefore, the impurity region 58 is not spread toward a transfer gate region under the word line 9 by diffusion of the injected ion through heat treatment.
(2) As shown in FIG. 5G, the opening 52 is formed in the resist film 50 through the photoengraving process in order to define the contact hole in the interlayer isolation film 48. However, since the exposure mask 54 is mechanically set for determining the position of the opening 52, misregistration (size L) of the exposure mask 54 based on mechanical accuracy cannot avoided. In other words, the contact hole must be located in consideration of overlay accuracy of the exposure mask 54.
In a DRAM of 4M, for example, allowance of about 0.6 .mu.m for diffusivity in paragraph (1), allowance of about 0.2 .mu.m (size L) for accuracy in mask alignment of paragraph (2) and actual allowance of 0.1 .mu.m, i.e., a distance of about 0.9 .mu.m in total is required between an end portion of the word line 9 and the side wall of the contact hole 49. Allowance of 0.8 .mu.m, in total, concerning paragraphs (1) and (2) has been a significant problem against improvement in degree of integration, in consideration of the fact that the width of the word line 9 is about 0.8 to 1.0 .mu.m.
Even if the said distance can be reduced in the conventional device, at least the occupied area for the contact part, which is basically provided on a flat part of the major surface of the semiconductor substrate, must be ensured. Thus, there has been a limit for improvement in degree and density of integration of the device.